View CT2566-FP_1557459.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

eroflex circuit t echnology ? data bus modules for the future ? scdct2566 rev b 8/10/99 features ? second source compatible to the bus-66300 ? pga version available, (second source to the bus-66312) ? compatible with mil-std-1750 cpus ? compatible with motorola, intel, and zilog cpus ? compatible with aeroflex?s ct2565 bc/rt/mt and ct2512 rt ? minimizes cpu overhead ? signal controls for shared memory implementation ? transfers complete messages to shared memory ? provides memory mapped 1553 interface ? packaging ? hermetic metal ? 78 pin, 2.1" x 1.87" x .25" pga type package ? 82 lead, 2.2" x 1.61 x .18" flat package description aeroflex ct2566 mil-std-1553 to microprocessor interface unit simplifies the cpu to 1553 data bus interface. the ct2566 provides an interface by using ram allowing the cpu to transmit or receive 1553 traffic simply by accessing the memory. all 1553 message transfers are entirely memory or i/o mapped. the ct2566 supports 1553 interface devices such as aeroflex's ct2512 dual rt or the ct2565 dual bc, rt, and mt. the ct2566 operates over the full military -55c to +125c temperature range. figure 1 ? functional block diagram ct2566 mil-std-1553 to microprocessor circuit technology www.aeroflex.com interface unit f i e i d c e r t a e r o f l e x l a b s i n c . iso 9001 clock in mstrclr select strbd readyd rd/ wr mem/ reg exten extld int ioen busreq busgrnt busack oe wr memoe memcs cs memwr adrinc nbgrnt bcstart tagen eom som msgerr timeout staterr looperr chb/ cha ctlinb/ a ctloutb/ a rtu/ bc mt dbac ssbusy ssflag svcreq reset operation control registers configuration register start / reset register interrupt mask register interrupt generator block status word microcode controller contention resolver memory timing timing cpu a15-a00 d15-d00
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 2 general the ct2566 was designed to perform required handshaking to the 1553 interface device, storing or retrieving message(s) from a user supplied ram and notifying the cpu that a 1553 transaction has occurred. the cpu uses this ram to read the received data as well as to store messages to be transmitted onto the bus. the ct2566 can be used to implement bc, rt, or mt operation and can be either memory mapped or i/o mapped to cpu address space. registers internal to the ct2566 control its operation. the ct2566 can access up to four external, user supplied registers and can address up to 64k words of ram. the ram selected must be a non-latched static ram (capable of meeting the timing constraints for the ct2566). a double buffering architecture is provided to prevent incomplete or partially updated information from being transmitted onto the 1553 data bus. the ct2566 requires an external, user supplied clock. compatible microprocessor types the ct2566 may be used with most common microprocessors, including, the motorola 68000 family, the intel 8080 family, zilog z8000 products, and available mil-std-1750 processors. interfacing the ct2566 to the 1553 data bus requires external circuitry such as aeroflex?s ct2565(bc/rt/mt) and act4489d transceivers. figure 2 shows the interconnection for these components. specifications at nominal power supply voltages parameter value units logic i ih (with v ih = 2.7v) - 630 a i il (with v il = 0.0v) - 700 a i oh 4.0 min ma i ol 4.0 ma v ih 2.0 v v il 0.8 v v oh 3.7 v v ol 0.4 v clock 12 mhz power supplies voltage 5.010% v current drain 10 typ ma temperature range operating (case) - 55 to +125 c storage - 65 to +150 c physical characteristics size 78 pin dip 2.1 x 1.87 x 0.25 (53 x 47.5 x 6.4) in (mm) 82 pin flatpack 2.1 x 1.87 x 0.25 (55.6 x 40.6 x 3.71) in (mm) weight 78 pin dip 1 (28) oz (g) 82 pin flatpack 1 (28) oz (g) table 1 ? specifications
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 3 pin no. name i/o description 1 select i select. when active, selects ct2566 for operation. 2 rd/ wr i read/write. controls cpu bus data direction. 3 readyd o ready data. when active indicates data has been received from, or is available to the cpu. 4 exten o external enable. output from ct2566 to enable output from external devices. same timing as memoe . 5 tagen o tag enable. enables an external time tag counter for transferring the time tag word into memory. 6 eom i end of message. input from 1553 device indicating end of message. 7 som i start of message. input from 1553 device indicating start of message in rtu mode. 8 staterr i status error. input from 1553 device when status word has either a bit set or unexpected rt address (in bc mode only). 9 adrinc i address increment. sent from 1553 device to increment address counter following word transfer. 10 mem/ reg i memory/register. input from cpu to select memory or register data transfer. 11 clock in i clock input; 50% duty cycle, 12mhz, max. 12 looperr i loop error. input from 1553 device if short loop bit fails. 13 busreq i bus request. when active, indicates 1553 device requires use of the address/data bus. 14 busgrnt o bus grant. handshake output to 1553 device in response to bus request indicating address/data bus available to 1553 device. 15 not used - - 16 memcs o memory chip select. low from ct2566 to enable external ram. used with 4k x 4 ram type device to read ram or used in conjunction with memwr to write data into ram. 17 oe i output enable. input from 1553 device used to enable memory on the parallel bus. 18 n/c - not used. 19 nbgrnt i low pulse from 1553 device preceding start of received new protocol sequence. used with superseding command to reset dma in progress. 20 + 5 volt i logic power supply. 21 d15 i/o data bus bit 15 (msb). 22 d13 i/o data bus bit 13. 23 d11 i/o data bus bit 11. 24 d09 i/o data bus bit 9. 25 d07 i/o data bus bit 7. 26 d05 i/o data bus bit 5. 27 d03 i/o data bus bit 3. table 2 ? pin functions (78 pin dip)
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 4 28 d01 i/o data bus bit 1. 29 ssflag o subsystem flag. output to 1553 device to set rt subsystem flag status bit. 30 ssbusy o subsystem busy. output to 1553 device to set rt subsystem busy flag. 31 rtu/ bc o output to 1553 device used in conjunction with mt to set operating mode. 32 a14 o address bit 14. 33 a12 o address bit 12. 34 a10 o address bit 10. 35 a08 o address bit 8. 36 a06 o address bit 6. 37 a04 o address bit 4. 38 a02 i/o address bit 2. 39 a00 i/o address bit 0 (lsb). 40 gnd - signal return. 41 strbd i strobe data. used in conjunction with select to indicate a data transfer cycle to/from cpu. 42 ioen o input/output enable. output from ct2566 to enable external buffers/latches connecting the hybrid to the address/data bus. 43 extld o external load. used to load data into external device via the ct2566 data bus. same timing as memwr . 44 chb/ cha input from 1553 in rt mode used to indicate received 1553 message came in either channel a or b. 45 int o interrupt. interrupt pulse line to cpu. 46 bcstart o bus controller start. outputs to 1553 in initiate bc cycle. 47 reset o reset. output to external device from ct2566 consisting of the or condition of cpu reset and cpu master clear. 48 msgerr i message error. input from 1553 device when an error occurs in message sequence. 49 ctlin b/ a i input to change active memory map area (0 = area a). 50 ctlout b/ a o output from ct2566 selecting which area is to be active (0 = area a). 51 timeout i input from 1553 device indicating no response time-out. 52 mstrclr i master clear. power-on reset from cpu. resets dma in progress and internal registers to logic ?0?. 53 busack i bus acknowledge. input from 1553 device acknowledge receipt of busgrnt . 54 wr i write. input from 1553 device for writing data into memory. 55 cs i chip select. input from 1553 device that is routed to memcs . pin no. name i/o description table 2 ? pin functions (78 pin dip) (cont.)
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 5 56 memoe o memory output enable. output from ct2566 to enable memory output data. 57 memwr o memory write. output pulse from ct2566 to write data bus data into memory. 58 not used - - 59 mt o bus monitor. used in conjunction with rtu/ bc to set operating mode. 60 d14 i/o data bus bit 14. 61 d12 i/o data bus bit 12. 62 d10 i/o data bus bit 10. 63 d08 i/o data bus bit 8. 64 d06 i/o data bus bit 6. 65 d04 i/o data bus bit 4. 66 d02 i/o data bus bit 2. 67 d00 i/o data bus bit 0 (lsb). 68 svcreq o service request. used to set service request bit in rt status word. 69 dbac o dynamic bus acceptance. used to set status bit in rt status word. 70 a15 o address bit 15 (msb). 71 a13 o address bit 13. 72 a11 o address bit 11. 73 a09 o address bit 9. 74 a07 o address bit 7. 75 a05 o address bit 5. 76 a03 o address bit 3. 77 a01 i/o address bit 1. 78 gnd - chassis ground. pin no. function pin no. function 1 n/c 42 n/c 2 select 43 ground 3 strbd 44 chassis ground 4 rd/ wr 45 a00 (lsb) 5 ioenbl 46 a01 6 readyd 47 a02 7 extld 48 a03 table 3 ? ct2566fp pin functions (82 pin flat package) pin no. name i/o description table 2 ? pin functions (78 pin dip) (cont.)
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 6 8 exten 49 a04 9 chb/ cha 50 a05 10 tagen 51 a06 11 int 52 a07 12 eom 53 a08 13 bcstart 54 a09 14 som 55 a10 15 reset 56 a11 16 staterr 57 a12 17 msgerr 58 a13 18 adrinc 59 a14 19 ctlin b/ a 60 a15 20 mem/ reg 61 rtu/ bc 21 ctlout b/ a 62 dbac 22 clock in 63 ssbusy 23 timeout 64 svcreq 24 looperr 65 ssflag 25 mstrclr 66 d00 26 busyreq 67 d01 27 busack 68 d02 28 busgrnt 69 d03 29 wr 70 d04 30 n/c 71 d05 31 cs 72 d06 32 memcs 73 d07 33 memoe 74 d08 34 oe 75 d09 35 memwr 76 d10 36 not used 77 d11 37 n/c 78 d12 38 nbgrnt 79 d13 39 mt 80 d14 40 +5v 81 d15 41 n/c 82 n/c pin no. function pin no. function table 3 ? ct2566fp pin functions (82 pin flat package) (cont.)
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 7 memory management the ram used by the ct2566 can be any standard static memory with a write strobe pulse width requirement less than 70ns. the ram area is broken down into pointers, look-up tables, and data blocks. all 1553 operation control is accomplished through the ram, including fault monitoring and data block transfers. for most applications, a 4k x 16 memory is sufficient to store the number of messages, but the ct2566 can access up to 64k words. double buffering a double buffering system is available to prevent partially updated data blocks from being read by the cpu or transferred onto the 1553 data bus. to use double buffering the cpu must divide the ram into two areas: ?current? and ?non-current?. two stack pointers, descriptor stacks, and look-up tables are required to be used by the cpu. the 1553 device has access only to the current area of ram, and will use the current descriptor stack and look-up table. while the 1553 device is processing messages using the current area pointers, the cpu can be setting up the next set of messages in the non-current area of ram. once an eom or bceom occurs, the cpu can swap the current and non-current areas by toggling bit 13 of the configuration register (see register section for description). the 1553 device will then have access to the new current area. meanwhile, the cpu can begin processing the data received during the previous transfer or can begin setting up the next set of 1553 messages. an external circuit (shown in figure 3) can be added to ensure that the swapping of the current and non-current areas doesn?t occur while the ct2566 is processing a message from the 1553 device. during message processing, the incmd is a logic "0" and the cpu?s map area selection is inhibited. ctlin b/ a will be automatically latched back into the ct2566 when incmd and nodt change to a logic "1". descriptor stack the ct2566 uses a descriptor stack in bc and rtu modes. each stack entry contains four words which refer to one 1553 message (see figure 4). the block status word, shown in figure 5, indicates the physical bus which received the message (rtu mode), reports whether or not an error was detected during message transfer, and indicates whether the message was completed (som replaced with eom). the user-supplied time-tag word is loaded at the start of a message transfer and is updated at the end of the transfer. the contents of the fourth word in the descriptor stack depends on the operating mode. in bc mode, it contains the address of the message data block containing the 1553 message formatted as shown in figure 6. in rtu mode, the word contains the received 1553 command word as shown in figure 7. a stack pointer must be initialized by the cpu. the descriptor stack contains 64, four word entries, and automatically wraps around (the 64th entry is followed by the first entry). the 1553 device uses the current area stack pointer to determine the address of the stack entry to be used for the current 1553 message. the ct2566 automatically increments the current area stack pointer by four upon the completion of each b u s - 6 6 3 0 0 c d q q figure 3 ? synchronized map switching u the ct2566 incmd nodt 12 mhz 50 ctlout b/ a 49 ctlin b/ a notes: (1) incmd is from the bus-65600 or bus-65112. (2) ctlout b/ a reflects bit 13 of the configuration register. (3) ctlin b/ a is used to select the current area. ls74 block status word time tag word reserved messabe block address bc description block block status word time tag word reserved received command word rtu description block figure 4 ? descriptor stack entries
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 8 message regardless of whether or not an error was detected during the processing of that message. look-up tables in rtu mode a look-up table is provided to allow the ct2566 to store messages in distinct areas of ram based upon the subaddress of the received command word. see rtu operation for details. the ct2566 uses the t/ r and the five subaddress bits to form a pointer into the ?current area? look-up table. the first 32 words of this table are initialized by the user with the addresses of the data blocks to be used for receiving data into subaddress 0,1,2,?31. the next 32 words are initialized by the user with the address of the data blocks to be used when transmitting data from subaddress 0,1,2,?31. ct2566 registers the ct2566 is controlled through the use of three internal registers: the interrupt mask register, configuration register, and start/reset register. in addition, the ct2566 can access up to four external, user supplied registers. possible external register applications include: defining the rtu address, storing a cpu time tag, and reading a captured built-in-test (bit) word from the 1553 interface unit. for further information, consult factory. table 2 ? internal registers address definition ct2566 address bits definition a2 a1 a0 0 0 0 interrupt mask register 0 0 1 configuration register 0 1 0 not used 0 1 1 start/reset register (write only) 1 0 0 external register 1 0 1 external register 1 1 0 external register 1 1 1 external register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 subsystem flag service request busy db accept stop on error control area bit b/ a mt rtu/ bc bit definitions subsystem flag 1553 status word bit. service request 1553 status word bit. busy 1553 status word bit. db accept 1553 status word bit. stop on error causes bc to stop at the end of current data block if an error is detected. control area b/ a used for double buffering (see double buffering). rtu/ bc /mt operating mode. bit 15 bit 14 mode 0 0 bc 0 1 mt 1 0 rtu 1 1 illegal figure 8 ? configuration register
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 loop test fail response time out (bc only) format error status set (bc only) error flag chb/ cha (rtu only) som eom note: in bc mode bit 13, chb/ cha contains a logic "0" regardless of which channel is used. note: (1) user may opt to share memory block(s). (2) see figure 19. figure 5 ? block status word figure 6 ? use of descriptor stack ? bc mode note: user may opt to share memory block(s). figure 7 ? use of descriptor stack ? rtu mode descriptor stacks stack pointers configuration register current area b/ a data blocks data block data block 0 13 15 block status word reserved time tag word message block addr descriptor stacks stack pointers configuration register current area b/ a data blocks data block data block 0 13 15 look-up table (data block addr) look-up table addr (2) (1) block status word reserved time tag word received command word
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 10 interrupt mask register this register is an eight bit read/write register used to enable the interrupt conditions. all interrupts are enabled with a logic "1" (see figure 9). start/reset register only two bits of this write only register are used, as illustrated in figure 10. 15 4 3 2 1 0 1 1 1 1 1 1 1 not used bc eom format error/status set not used eom interrupt definition eom end of message. set by ct2566 (during bc or rtu mode) every time a 1553 message is transferred (regardless of validity). format error/ set by ct2566 for these conditions: status set loop test failure: last transmitted word did not match received word. message error: received message contained an address error, one of eight 1553 status bits set, or 1553 specification violated (parity error, manchester error, etc). time-out: expected transmission was not received during allotted time status set: received status word contained status bit(s) set or address error. bc eom bus controller end of message. set by ct2566 (in bc mode) when all messages have been transferred. figure 9 ? interrupt mask register 15 1 0 not used controller start reset bit definition reset issued by the cpu to place the ct2566 in the power-on condition; configuration, and interrupt mask registers are reset to logic ?0?. controller start issued by the cpu (bc mode) to start message transmission. the cpu must first load the number of messages to transfer (256, max) in the message count location of ram (area a or b). value is loaded in 1?s complement (load fffe to transmit one message). in mt mode it is used to begin reception of 1553 messages. issued by cpu in mt mode to enable monitor operation. figure 10 ? start/reset register
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 11 bc operation the bc mode is selected by setting the two msbs of the configuration register to logic "0". this can be done by writing directly to the register or by issuing a mstrclr or reset command. note that a reset will also clear the interrupt mask register. bc initialization. for bc operation, the user initializes the ram as shown in table 3 and follows the steps in figure 11, bc initialization. the cpu loads the data blocks with 1553 messages (see figure 12). the first word of each data block must contain the control word (shown in figure 13) for the message. the starting addresses of the data blocks are placed in the fourth word of the descriptor stack in the order the messages are to be transmitted (i.e. the address of the first message is loaded into the fourth location of the stack, the address of the second message is placed into the eighth location, etc). once the data blocks and the descriptor stack have been initialized, the cpu loads the current area message count with the number of messages to transfer (load in 1?s complement). table 3 - typical bc memory map (4k memory)] hex address function fixed areas 0100 stack pointer a 0101 message count a 0104 stack pointer b 0105 message count b user defined areas 0108-013f not used 0140-017f data block 1 0180-01bf data block 2 01c0-01ff data block 3 ? ? ? ? 0f00-0fff descriptor stack a 0000-00ff descriptor stack b control word control word control word control word control word control word receive command transmit command receive command mode command transmit command broadcast command control word mode command mode command data word 1 data word 2 data word last status word status word status word data word 1 data word 2 data word last data word 1 data word 2 data word last status receive data word 1 received data word 2 received data word data word received status received status word 1 from xmtr status word 2 receiver from terminal to terminal last data word received data word looped ct2565 back by remote remote data block command back by transmit looped ct2565 command back by broadcast looped ct2565 command back by mode looped ct2565 command back by mode looped ct2565 data word back by looped ct2565 last back by data word looped ct2566 transmit data block receive data block with data data block mode code transmit format command back by transmit looped ct2565 with data data block mode code receive format mode code without data broadcast command with data broadcast command (no data) broadcast command (no data) figure 12 ? bc message data block formats
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 12 the cpu selects an internal register by asserting mem/ reg and the a2 bit to logic "0" (see table 2). external registers are selected by asserting mem/ reg logic "0" and a2 bit to a logic "1". the signals exten and extld are used to read and write from the external registers (see figures 26 to 28). configuration register the configuration register is an eight bit read/write register used to define the 1553 operating mode (bc, mt, or rtu) and the associated rtu status bits. the four msbs define the mode of operation; the four lsbs define the rtu status bits (see figure 8). all bits in the configuration register (except bit 12) will be present on the respective ct2566 output pins to the 1553 device. the mt bit is inverted at the output. to begin transferring messages onto the bus, the cpu must issue a controller start command (see figure 14). this is done by setting bit 1 of the start/reset register to a logic "1". an eom interrupt will be generated each time a message transfer has been completed. a bceom will be generated once the specified number of messages has been transferred (message counter = ffff). a format error status set interrupt will be generated at the end of a message if a timeout condition or error condition was detected. if the stop on error bit in the configuration register is set, the ct2566 will stop bus transactions until a new controller start command is issued by the cpu. these interrupts may be masked by the cpu through the interrupt mask register. bc start sequence after setting the controller start bit in the start/reset register, the ct2566 takes the following actions: 1. reads the stack pointer to get the address of the current descriptor stack entry. 2. stores an som flag in the block status word to indicate a transfer operation is in progress. 3. stores the time tag if used. 4. reads the data block address from the fourth location of the descriptor stack and transfers the data block address into an internal address register. 5. issues a bcstart pulse to the associated 1553 device to start the message transfers. note that data words are transferred to an from memory by the associated 1553 interface unit using the internal address register. bc eom sequence. upon completion of a 1553 message (valid or invalid) the 1553 interface unit issues an eom pulse to the ct2566 which takes the following actions: 1. reads the stack pointer to get the address of the current descriptor stack entry. 15 8 7 0 not used bus channel a/ b not used mask broadcast bit not used mode code broadcast rtu to rtu note: when the bc expects the broadcast bit set in the status word, a logic "1" will mask the status interrupt error flag. a format error will be generated if the mask broadcast bit is not set. issue reset command initialize stack pointer load message counter load messages issue start command set configuration resister to bc mode initialize interrupt mask register load every fourth location of stack with starting address start figure 11 bc initialization (under user control) figure 13 ? bc control word
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 13 controller start command received reads stack pointer load block status word into first word of descriptor stack entry (set som bit in block status word) load time tag into second word of descriptor stack entry address from fourth word obtain data block issue bc start to 1553 device determine type of transfer read control word to update block status word update time tag increment stack pointer by four. decrement message count transferred ok data block ? transferred ok stop on ? error set yes no no yes no more messages ? to send yes issue bc eom stop figure 14 ? bc sequence of operation (under ct2566 control) transfer data to/from 1553 bus (note: ram now controlled by input pins cs and oe * * after controller start is issued the subsystem must wait until bceom is active before issuing the next controller start.
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 14 2. updates the block status word by resetting the som and setting eom and any error bits. 3. updates the time tag if used. 4. increments the contents of the stack pointer by four and increments the message counter by one. 5. initiates a message transfer beginning with new controller start sequence if more messages are to be transmitted. 6. generates a bceom interrupt if enabled and no further messages are to be transmitted. note that if an error is received and stop on error is set, the ct2566 completes the current bceom sequence and then stops. the stack pointer will point to the next message to be transmitted. rtu operation the rtu mode is selected by setting bit 15 of the configuration register to logic "1" and bit 14 to logic"0". rtu initialization for rtu operation, the user initializes the ram as shown in table 4 and follows the steps shown in figure 15, rtu initialization chart. look-up tables the first 32 words of the look-up table are initialized with the addresses of the data blocks to be used when received data from subaddress 0, 1, 2,?31. the next 32 table locations should be initialized with the address of the data blocks to be used when the rtu is instructed to transmit data from subaddress 0, 1, 2,?31. the data blocks may be any length sufficient to contain the particular message as long as the data block does not cross a 256 word boundary. data blocks may be shared by look-up tables a and b, if desired by the user (see figure 16). the 1553 device can only access the current look-up table and the current descriptor stack. the cpu selects the current area through bit 13 of the configuration register. once in the rtu mode, the ct2566 will store the command word in the fourth location of the current area descriptor stack. the status of the message will be recorded in the first location of the stack. the data associated with the message will be transferred to/from the data block indicated by the look-up table entry for that subaddress. if a system time tag is provided by the user the ct2566 will record the time of the som sequence in the second word of the stack entry. when the ct2566 received an eom pulse from the 1553 device, it resets the som bit in the block status word and sets the eom bit and any error bits as necessary. the time tag entry will be updated and an eom interrupt will be generated by the cpu, if enabled. rtu som sequence initiated when 1553 terminal puts a 1553 command word on d00-d15 and pulses som low. the ct2566 saves the command received in an internal register. figure 17 illustrates the rtu sequence of operation once a 1553 command word is received. once the command word is received, the ct2566 performs the following steps: 1. reads the stack pointer to get the address of the current descriptor stack entry. 2. stores a som flag in the block status word to indicate a transfer operation is in progress. 3. stores the time tag if used. table 4 ? typical rtu memory map (4k memory) hex address function fixed areas 0100 descriptor stack pointer a 0101 reserved 0104 descriptor stack pointer b 0105 reserved 0108-013f spare 0140-017f look-up table a 01c0-01ff look-up table b user defined areas 0180-019f data block 1 01a0-01bf data block 2 0200-021f data block 3 0220-023f data block 4 0240-025f data block 5 0260-027f data block 6 ? ? ? ? 0ee0-0eff data block 107 0000-00ff descriptor stack a 0f00-0fff descriptor stack b 15 8 7 6 5 4 0 0 0 0 0 0 0 0 0 1 current area b/ a (config. reg bit 13) t r (from command word) rtu subaddress bits (from command word) rtu look-up table address
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 15 4. stores the command word received. 5. reads a block address from the look-up table using the t/ r bit and the subaddress from the command word; transfers the block address into the address register. data words are transferred to/from memory by the associated 1553 interface unit using the address register. rtu eom sequence at the end of a 1553 message (valid or invalid) the ct2566 received an eom pulse and then performs the following: 1. updates the block status word. 2. updates the time stage if used. 3. increments the stack pointer by four. 4. generates an error interrupt if enabled. figure 17 ? rtu sequence of operation (under ct2566 control) message complete generate eom interrupt and condition detected error interrupt if error increment stack pointer by four update block status word and time tag transfer data to/from 1553 interface device read look-up table using area bit b/ a t/ r subaddress current update descriptor stack tag and command word block status word, time read stack pointer 1553 command word received exit ? no yes received command word look-up table rtu addr t/ r subadd word count xxxxx 0 00000 xxxxx user defined 0140 64 locations user defined xxxxx 0 00001 xxxxx 0141 user defined xxxxx 0 00010 xxxxx 0142 xxxxx 1 11110 xxxxx user defined 017e user defined xxxxx 1 11111 xxxxx 017f } figure 16 ? rtu look-up table start issue reset command initialize stack pointer set up data blocks wait for 1553 command set up look-up table(s) data block assignments figure 15 rtu initialization (under user control) initialize interrupt mask register set configuration register to rtu mode
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 16 mt operation the mt mode is selected by setting bit 15 of the configuration register to logic "0" and bit 14 to a logic"1" along with issuing a controller start command. mt initialization for mt operations, the entire ram is used as the mt stack (see table 5) and the setups shown in figure 18 are followed. the user instructs the ct2566 where to store the first received 1553 word by loading the starting word address in the stack pointer. once a controller start command is issued, the ct2566 will store this value in the internal address register. the identification word provides the cpu with additional information regarding the received 1553 word, its format is shown in figure 19. this information allows the user to develop algorithms to restructure the message transfers. external logic can be used for triggering on specific commands or subaddresses. for further information, consult factory. the 1553 device will generate an identification word for every word that is transferred across the 1553 data bus. the ct2566 stores the received 1553 word in the ram location indicated by the internal address register. the contents of this register are incremented by one so that it points to the next word in ram, and the identification word is stored at that location. the internal address register is then incremented by one again, in preparation for storing the next identification word. the ram automatically wraps around (from location ffff to location 0000), shown in figure 20. bit 7 of the identification word can be reset by the cpu each time it reads the associated data word into cpu memory. this provides a simple method of keeping track of words that have been processed by the cpu. start issue reset command clear ram initialize stack pointer set configuration register to mt mode issue start command figure 18 ? mt initialize (under user control) 15 8 7 0 1 1 1 1 gap time set to "1" error (1 = error, 0 = good status) command sync 1553 channel a/ b word gap set to "0" note: each bit of the gap time field represents .5s. figure 19 ? mt identification word get stack pointer from word 100 in ram and store in internal register start command issued store retreived 1553 word in ram, increments internal address register figure 20 ? mt sequence of operation (under ct2566 control) store identification word in ram, increment internal address register no word transferred across 1553 bus ? yes
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 17 ct2566 timing clock in at 12 mhz figures 21 through 37 illustrate the timing for the ct2566 and its operation. all timing definitions are listed in the tables below and the appropriate definitions are repeated with each diagram. table 5 ? typical mt memory map (4k memory) hex address function 0000 first received 1553 word mode codes all mode codes applicable to dual redundant systems are recognized by the ct2566. mode codes can be illegalized by the 1553 bc or rtu device. refer to the ct2565 or ct2512 data sheets for more information. 0001 first identification word 0002 second received 1553 word 0003 second identification word 0004 ? 0005 ? 0006 ? 0007 ? 0008 ? ? ? ? ? 0100 stack pointer a (fixed location)* 0104 stack pointer b ? ? ? ? ffff word stored at ffff will be followed by the word stored at 0000. * the stack pointer is loaded into an internal address register upon receipt of a controller start command. this location is overwritten by data once monitor operation begins. delay timing symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns td3 cpu memwr low delay - 120 ns td4 cpu memoe low delay - 115 ns td5 extld low delay - 130 ns td6 reset low delay - 30 ns td7 internal register delay (read) - 60 ns td8 internal register delay (write) - 60 ns td9 register data/address set-up time - 40 ns td10 register data/address hold time - 0 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 18 td11 bc som cycle dma delay - 120 ns td12 int low delay - 50 ns td13 rtu som cycle dma delay - 200 ns td14 1553 command word set-up time 60 - ns td15 1553 command word hold time 60 - ns td16 mt som cycle dma delay - 120 ns td17 cs low to memcs low delay - 30 ns td18 oe low to memoe low delay - 30 ns td19 wr low to memwr low delay - 30 ns td20 busgrnt high delay - 25 ns td21 busack low address delay - 45 ns td22 busack high address delay - 25 ns td23 address increment delay - 200 ns pulse width timing symbol description min max units tpw1 readyd pulse width (cpu handshake) 70 - ns tpw2 cpu memwr low pulse width 70 - ns tpw3 cpu memcs low pulse width 70 - ns tpw4 extld low pulse width 70 - ns tpw5 reset low pulse width 70 - ns tpw6 dma memwr low pulse width 70 - ns tpw7 dma memcs low pulse width 70 - ns tpw8 bcstart low pulse width 70 - ns tpw9 eom low pulse width 50 200 ns tpw10 int low pulse width * tpw9 ns tpw11 int low (bceom) pulse width 60 - ns tpw12 som low pulse width 50 200 ns tpw13 nbgrnt low pulse width 50 200 ns tpw14 adrinc low pulse width 50 200 ns tpw15 mstrclr low pulse width 150 - ns * the min value of tpw10 equals tpw9 minus 30 ns. delay timing (cont.) symbol description min max units
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 19 a02 (38) a01 (77) a00 (39) ssflag , ssbusy , svcrqst dbac , rtu/ bc , mt , ctlinb/ a mem/ reg (10) d15-d00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note data valid td1 tpw1 td2 td7 figure 21 ? cpu reads from internal register note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu reads from internal register symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td7 internal register delay (read) - 60 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 20 a02 (38) a01 (77) a00 (39) ssflag , ssbusy , svcrqst dbac , rtu/ bc , mt , ctlinb/ a mem/ reg (10) d15-d00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 td2 td9 tpw1 td8 td10 data latched configuration register only data valid figure 22 ? cpu writes to internal register note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu writes to internal register symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td8 internal register delay (write) - 60 ns td9 register data/address set-up time - 40 ns td10 register data/address hold time - 0 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 21 a02 (38) a01 (77) a00 (39) mem/ reg (10) d15-d00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 td9 tpw1 data from external register exten (4) td2 figure 23 ? cpu reads from external register note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu reads from external register timing symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td9 register data/address set-up time - 40 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 22 a02 (38) a01 (77) a00 (39) mem/ reg (10) d15-d00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 td9 tpw1 cpu data extld (43) td10 valid valid tpw4 td5 td2 figure 24 ? cpu writes to external register note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu writes to external register symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td5 extld low delay - 130 ns td9 register data/address set-up time - 40 ns td10 register data/address set-up time - 0 ns tpw4 extld low pulse width 70 - ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 23 memoe (56) mem/ reg (10) a15-a00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 tpw1 d15-d00 td2 ram address valid td4 ram data valid memcs (16) figure 25 ? cpu reads from ram note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu reads from ram symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td9 cpu memoe low delay - 115 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 24 memwr (57) mem/ reg (10) a15-a00 ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 tpw1 d15-d00 td2 ram address valid td3 ram data valid memcs (16) tpw2 tpw3 figure 26 ? cpu writes to ram note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. cpu writes to ram symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns td3 cpu memwr low delay - 120 ns tpw2 cpu memwr low pulse width 70 - ns tpw3 cpu memcs low pulse width 70 - ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 25 td2 busgrnt (14) td22 td20 a15-a00 busack (53) busreq (13) cs (55) memcs (16) oe (17) memoe (56) wr (54) memwr (57) td18 td19 td17 figure 27 ? mil-std-1553 to ct2566 handshaking figure 28 ? mil-std-1553 terminal i/o delay mil-std-1553 to ct2566 handshaking symbol description min max units td20 busgrnt high delay - 25 ns td21 busack low address delay - 45 ns td22 busack high address delay - 25 ns mil-std-1553 terminal to delay symbol description min max units td17 cs low to memcs low delay - 30 ns td18 oe low to memoe low delay - 30 ns td19 wr low to memwr low delay - 30 ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 26 td23 a15-a00 busack (53) adrinc (9) address address + 1 td14 mstrclr (52) reset (47) tpw15 td6 see note figure 29 ? ct2566 unit address increment figure 30 ? ct2566 direct reset ct2566 direct increment symbol description min max units td6 reset low delay - 30 ns tpw15 mstrclr low pulse width 150 - ns ct2566 address increment symbol description min max units tpw14 adrinc low pulse width 50 200 ns td23 address increment delay - 200 ns note: the reset (low) pulse width will be approximately equal to that of mstrclr (low).
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 27 a02 (38) a01 (77) ioen (42) select (1) strbd (41) (internal) 12mhz clock rd/ wr (2) readyd (3) see note td1 tpw1 td2 reset (47) d00 (67) a00 (39) mem/reg 10) tpw5 figure 31 ? programmed ct2566 reset note: strbd to ioen (low) delay is two clock cycles. if contention occurs, delay is two clock cycles following release of bus. programmed ct2566 reset symbol description min max units td1 readyd low delay (cpu handshake) - 200 ns td2 ioen high delay (cpu handshake) - 20 ns tpw1 readyd pulse width (cpu handshake) 70 - ns tpw5 reset low pulse width 70 - ns
a e r o f l e x c i r c u i t t e c h n o l o g y s c d c t 2 5 6 6 r e v b 8 / 1 0 / 9 9 p l a i n v i e w n y ( 5 1 6 ) 6 9 4 - 6 7 0 0 2 8 a15-a00 td10 td11 td9 stack address stack address + 1 d15-d00 bcstart (46) tagen (5) memoe (56) memwr (57) memcs (16) readyd (3) ioen (42) select (1) a00 (39) a01 (77) a02 (38) rd/ wr (2) mem/ reg (10) d01 (28) strbd (41) (internal) 12 mhz clock block status word time tag tri-state stack address + 2 stack pointer stack address block address stack address + 3 tpw8 figure 32 ? bc som timing (no contention) bc som timing (no contention) symbol description min max units td9 register data/address set-up time - 40 ns td10 register data/address hold time - 0 ns td11 bc som cycle dma delay - 120 ns tpw8 bcstart low pulse width 70 - ns
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 29 figure 33 ? bc eom timing (no contention) (internal) 12 mhz clock a15-a00 stack address + 2 stack address + 3 stack address + 1 stack address stack pointer tri-state tri-state time tag block status word stack address td12 tpw10 d15-d00 int (45) tagen (5) memoe (56) memwr (57) memcs (16) eom (6) tpw9 eom/error figure 33 ? bc eom timing (no contention) con?t tri-state stack address + 4 tpw11 bc message count stack pointer stack pointer + 1 stack pointer + 2 stack pointer + 1 message count + 1 eom bc eom timing (no contention) symbol description min max units td9 int low delay - 50 ns tpw9 int low pulse width 50 200 ns tpw10 int low pulse width * tpw9 ns tpw11 int low delay 60 - ns * the min value of tpw10 equals tpw9 minus 30ns.
a e r o f l e x c i r c u i t t e c h n o l o g y s c d c t 2 5 6 6 r e v b 8 / 1 0 / 9 9 p l a i n v i e w n y ( 5 1 6 ) 6 9 4 - 6 7 0 0 3 0 bcstart (46) tagen (5) memoe (56) memwr (57) memcs (16) som (7) td13 a15-a00 stack pointer d15-d00 stack address + 1 stack address + 3 stack address + 2 stack address look-up address stack address block status word time tag tri-state command block address 1553 command word tpw8 tpw12 tpw13 td15 td14 nbgrnt (19) figure 34 ? rtu som (no contention) rtu som timing (no contention) symbol description min max units td13 rtu som cycle dma delay - 200 ns td14 1553 command word set-up time 60 - ns td15 1553 command word hold time 60 - ns tpw8 bcstart low pulse width 70 - ns tpw12 som low pulse width 50 200 ns tpw13 nbgrnt low pulse width 50 200 ns
a e r o f l e x c i r c u i t t e c h n o l o g y s c d c t 2 5 6 6 r e v b 8 / 1 0 / 9 9 p l a i n v i e w n y ( 5 1 6 ) 6 9 4 - 6 7 0 0 3 1 figure 35 ? rtu eom timing (no contention) (internal) 12 mhz clock tpw10 int (45) tagen (5) memoe (56) memwr (57) memcs (16) eom (6) tpw9 a15-a00 stack address + 2 stack address + 3 stack address + 1 stack address stack pointer tri-state tri-state time tag block status word stack address d15-d00 stack address + 4 stack pointer rtu eom timing (no contention) symbol description min max units tpw9 reset low delay 50 200 ns tpw10 mstrclr low pulse width * tpw9 ns * the min value of tpw10 equals tpw9 minus 30ns.
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 32 figure 36 ? mt som timing (no contention) mt som timing (no contention) symbol description min max units td16 mt som cycle dma delay - 120 ns tpw6 bcstart low pulse width 70 - ns stack address (internal) 12 mhz clock tpw6 d01 (28) select (1) d15-d00 a15-a00 bcstart (46) memoe (56) memcs (16) readyd (3) ioen (42) strbd (41) a00 (39) a01 (77) rd/ wr (2) mem/ reg (10) a02 (38) stack pointer td16
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 33 figure 37 ? dma read/write timing (som/eom cycles) dma read/write timing (som/eom cycles) symbol description min max units tas1 dma address set-up time 40 - ns tah1 dma address hold time 60 - ns tds1 dma address set-up time 83 - ns tdh1 dma address hold time 30 - ns tas2 dma address set-up time - 45 ns tah2 dma address hold time 0 - ns tds2 dma address set-up time - 83 ns tdh2 dma address hold time 0 - ns tpw6 dma memwr low pulse width 70 - ns tpw7 dma memcs low pulse width 70 - ns dma read dma write tdh2 a15-a00 tds2 tas2 12 mhz clock memwr (57) memoe (56) memcs (16) (internal) d15-d00 tah2 tas1 tpw7 tpw6 tah1 tdh1 tds1
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 34 21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40 1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20 select strbd rd/ wr ioen readyd extld exten chb/ cha tagen int eom bcstart som reset staterr msgerr adrinc ctlin b/ a mem/ reg ctlout b/ a clock in timeout looperr mstrclr busreq busack busgrnt wr n/c cs memcs memoe oe memwr n/c n/c nbgrnt mt +5 volt d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 ssflag svcreq ssbusy dbac rtu/ bc a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00 gnd gnd ct2566 mil-std-1553 to processor interface unit ddip pin connection diagram, ct2566 and pinout table 6 ? ct2566 pin out description (ddip) pin # function pin # function 1 select 40 gnd 2 rd/ wr 41 strbd 3 readyd 42 ioen 4 exten 43 extld 5 tagen 44 chb/ cha 6 eom 45 int 7 som 46 bcstart 8 staterr 47 reset 9 adrinc 48 msgerr 10 mem/ reg 49 ctlin b/ a 11 clock in 50 ctlout b/ a 12 looperr 51 timeout 13 busreq 52 mstrclr 14 busgrnt 53 busack 15 n/c 54 wr 16 memcs 55 cs 17 oe 56 memoe 18 n/c 57 memwr 19 nbgrnt 58 n/c 20 + 5 volt 59 mt 21 d15 60 d14 22 d13 61 d12 23 d11 62 d10 24 d09 63 d08 25 d07 64 d06 26 d05 65 d04 27 d03 66 d02 28 d01 67 d00 29 ssflag 68 svcreq 30 ssbusy 69 dbac 31 rtu/ bc 70 a15 32 a14 71 a13 33 a12 72 a11 34 a10 73 a09 35 a08 74 a07 36 a06 75 a05 37 a04 76 a03 38 a02 77 a01 39 a00 78 gnd
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 35 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 select strbd rd/ wr ioenbl readyd extld exten chb/ cha tagen int eom bcstart som reset staterr msgerr adrinc ctlin b/ a mem/ reg ctlout b/ a clock in timeout looperr mstrclr busyreq busack busgrnt wr n/c cs memcs memoe oe memwr n/c n/c nbgrnt mt +5v d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 ssflag svcreq ssbusy dbac rtu/ bc a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00 (lsb) case gnd ground table 7 ? ct2566 pin out description (fp) pin # function pin # function 1 n/c 42 n/c 2 select 43 ground 3 strbd 44 case gnd 4 rd/ wr 45 a00 (lsb) 5 ioenbl 46 a01 6 readyd 47 a02 7 extld 48 a03 8 exten 49 a04 9 chb/ cha 50 a05 10 tagen 51 a06 11 int 52 a07 12 eom 53 a08 13 bcstart 54 a09 14 som 55 a10 15 reset 56 a11 16 staterr 57 a12 17 msgerr 58 a13 18 adrinc 59 a14 19 ctlin b/ a 60 a15 20 mem/ reg 61 rtu/ bc 21 ctlout b/ a 62 dbac 22 clock in 63 ssbusy 23 timeout 64 svcreq 24 looperr 65 ssflag 25 mstrclr 66 d00 26 busyreq 67 d01 27 busack 68 d02 28 busgrnt 69 d03 29 wr 70 d04 30 n/c 71 d05 31 cs 72 d06 32 memcs 73 d07 33 memoe 74 d08 34 oe 75 d09 35 memwr 76 d10 36 n/c 77 d11 37 n/c 78 d12 38 nbgrnt 79 d13 39 mt 80 d14 40 +5v 81 d15 41 n/c 82 n/c ct2566fp mil-std-1553 to processor interface unit flat package pin connection diagram, ct2566 and pinout 1 2 n/c n/c n/c n/c 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 82 81
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 36 .100 2.100 1.500 typ lead 1 & esd designator 1.900 1.800 pin 19 pin 20 pin 59 pin 41 pin 2 .050 typ 1.650 1.870 .100 .110 pin 1 .250 .250 max pin 39 pin 40 pin 78 pin 22 pin 21 pin 60 .018 dia typ .080 .180 max .010 .002 .015 2.000 pin 42 .095 pin 41 2.200 max lead 1 & esd designator 1.610 max designator max .400 min .050 lead centers 41 leads/side (4 places) pin 82 flat package outline plug in package outline .050
aeroflex circuit technology scdct2566 rev b 8/10/99 plainview ny (516) 694-6700 37 circuit technology aeroflex circuit technology 35 south service road plainview new york 11803 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: (800) the-1553 specifications subject to change without notice www.aeroflex.com/act1.htm e-mail: sales-act@aeroflex.com ordering information model number screening desc smd # package ct2566 military temperature, -55c to +125c, screened to the individual test methods of mil-std-883 - plug in CT2566-FP - flat package

▲Up To Search▲

Price & Availability of CT2566-FP

	To Download CT2566-FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .